부산대학교 도서관

This work presents a novel multiplier design methodology with an electro-optic mixed structure based on time-domain accumulation. Especially, it employs complementary metal oxide semiconductor (CMOS) logic gates to generate partial products in electrical domain because of the simplicity of Boolean operation with low hardware overhead. Then, an optical delay accumulation (ODA) structure is proposed to accumulate all partial products in time-domain, to avoid the issues of logic cascadability, fan-out and power loss encountered in prior all-optical and optical-directed logic-based multipliers. At last, a time-to-digital converter (TDC) is presented to generate the final product back in a digital value. To verify the functionality and evaluate the performance, an 8-bit electro-optic mixture structure multiplier is developed and simulations show that the proposed design can operate at 20 GHz and the average computation delay is 1.25 ns with 28 nm CMOS process and compatible silicon optical device. The time consumption is reduced by 37.8% in average compared with the electrical Shift-and-Add multiplier. In addition, for 8-bit, 16-bit and 32-bit multipliers, the proposed multiplier can reduce optical device cost by 99.01%, 99.59%, and 99.82% respectively, as well as decrease power loss by 79%, 79% and 81% compared to prior optical designs.