부산대학교 도서관

Summary form only given. Semiconductor systems, whether cell-phones, laptops, servers or machine learning accelerators, require an increasing number of processing units, larger caches and faster interfaces while managing cost and power dissipation. As we continue to push the transistor, interconnect and memory scaling to smaller geometries, the industry is moving quickly towards 3D heterogeneous integration for higher density, performance and faster time-to-market. This presentation will review recent market trends and focus on advances in process scaling for libraries, memories and external interfaces. We will cover several design and technology co-optimization (DTCO) techniques that enable higher transistor density and performance. One example is the 2D fin depopulation from 4 to 3 and more recently 2 fins. We will also explore heterogeneous integration, where complex systems are partitioned into multiple chiplets that are assembled in 2.5D or 3D topologies. In particular, we will discuss 3D integration performance and energy improvements, as well as mitigation techniques for cooling and yield challenges.