학술논문
Modeling intrinsic and extrinsic asymmetry of 3D cylindrical gate/gate-all-around FETs for circuit simulations
Document Type
Conference
Source
2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding Non-Volatile Memory Technology Symposium (NVMTS), 2011 11th Annual. :1-4 Nov, 2011
Subject
Language
Abstract
In a vertical cylindrical gate transistor, we identify doping gradation along channel and structural difference in electrode regions as major reasons for highly asymmetric drain current characteristics. These effects have been captured in a physical manner in a SPICE model. Calibration results of such a model to silicon device data from a vertical cylindrical gate technology that exhibits asymmetric I-V characteristics is presented for the first time.