학술논문

Implementation of CNFET based Negative Gain Digitally Programmable Current Conveyor
Document Type
Conference
Source
2022 5th International Conference on Multimedia, Signal Processing and Communication Technologies (IMPACT) Multimedia, Signal Processing and Communication Technologies (IMPACT), 2022 5th International Conference on. :1-5 Nov, 2022
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Fields, Waves and Electromagnetics
Signal Processing and Analysis
Semiconductor device modeling
Performance evaluation
Resistance
Semiconductor device measurement
Current measurement
Bandwidth
Signal processing
current conveyor
digitally programmable current conveyor with negative gain
CMOS and CNFET
Language
Abstract
This paper presents simulation study of 32 nm carbon nanotube field effect transistor (CNFET) and complementary metal oxide semiconductor (CMOS) based negative gain digitally programmable second generation current conveyor (DPCCIIK - ). A thorough analysis of negative gain CNFET (CN-DPCCIIK - ) and CMOS based DPCCIIK - (CMOS-DPCCIIK - ) for various specifications characteristics like voltage and current bandwidth, negative current gain, voltage gain, average power, and terminal X and Y resistances has been done. Thus, from obtained results it has been observed that the bandwidth of CN-DPCCIIK - has been increased considerably by 10 3 fold. Average power dissipated by CN-DPCCIIK - is 77 % lower than CMOS-DPCCIIK - . Other performance measuring parameters like terminal X of CN-DPCCIIK - is 99% lower than its CMOs counterpart. Terminal Y resistance of CN-DPCCIIK - is 362 times more than CMOS-DPCCIIK - . It has been observed that CN-DPCCIIK - satisfies the desired characteristics a DPCCIIK - with minimized area. Entire simulation has been done at ±0.7V using HSPICE at 32 nm technology node.