학술논문

Temporal isolation on multiprocessing architectures
Document Type
Conference
Source
2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC) Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE. :274-279 Jun, 2011
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Communication, Networking and Broadcast Technologies
Instruction sets
Computer architecture
Interference
Timing
Real time systems
Random access memory
Hardware
Precision-timed architectures
PRET machines
microarchitecture
pipelines
memory hierarchy
network on chip
instruction set architecture
Language
ISSN
0738-100x
Abstract
Multiprocessing architectures provide hardware for executing multiple tasks simultaneously via techniques such as simultaneous multithreading and symmetric multiprocessing. The problem addressed by this paper is that even when tasks that are executing concurrently do not communicate, they may interfere by affecting each others' timing. For cyberphysical system applications, such interference can nullify many of the advantages offered by parallel hardware and can enormously complicate synthesis of software from models. This paper examines what changes need to be made at lower levels of ab]ion to support temporal isolation for effective software synthesis. We discuss techniques at the microarchitecture level, in the memory hierarchy, in on-chip communication, and in the instruction-set architecture that can facilitate temporal isolation.