학술논문
A disruptive computer design idea: Architectures with repeatable timing
Document Type
Conference
Author
Source
2009 IEEE International Conference on Computer Design Computer Design, 2009. ICCD 2009. IEEE International Conference on. :54-59 Oct, 2009
Subject
Language
ISSN
1063-6404
Abstract
This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.