학술논문

Study on Failure Mechanism of C4 Bump Solder Excursion in CoWoS Package
Document Type
Conference
Source
2024 Conference of Science and Technology for Integrated Circuits (CSTIC) Science and Technology for Integrated Circuits (CSTIC), 2024 Conference of. :1-3 Mar, 2024
Subject
Bioengineering
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Photonics and Electrooptics
Integrated circuits
Semiconductor device modeling
Moore's Law
Failure analysis
Packaging
Reflectometry
Market research
Solder excursion
CoWoS (Chip on Wafer on Substrate)
Under-fill delamination
Time Domain Reflectometry (TDR)
Language
Abstract
As Moore's Law reaches its limit, the trend of chip development towards advanced packaging is becoming increasingly evident, with Chip on Wafer on Substrate (CoWoS) packaging (2.5D) technology rapidly being adopted by major IC manufacturers due to its advantages. However, the structure of CoWoS package is more complex than other package, its failure analysis (FA) also facing many challenges. This paper analysis the solder excursion of C4 bump and study its failure mechanism in CoWoS package. The flux residue comes from the substrate causes delamination between the solder mask (SM) and under-fill, resulting in solder excursion.