학술논문
Chip-level characterization and RTN-induced error mitigation beyond 20nm floating gate flash memory
Document Type
Conference
Author
Source
2018 IEEE International Reliability Physics Symposium (IRPS) Reliability Physics Symposium (IRPS), 2018 IEEE International. :P-MY.6-1-P-MY.6-5 Mar, 2018
Subject
Language
ISSN
1938-1891
Abstract
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a “Gaussian-like” shape rapidly and was measured by the self-established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.