학술논문

Interpretable Neural Network to Model and to Reduce Self-Heating of FinFET Circuitry
Document Type
Conference
Source
2020 IEEE Symposium on VLSI Technology VLSI Technology, 2020 IEEE Symposium on. :1-2 Jun, 2020
Subject
Components, Circuits, Devices and Systems
Testing
Artificial neural networks
Training
SPICE
Integrated circuit modeling
Layout
Logic gates
Language
ISSN
2158-9682
Abstract
An interpretable neural network (NN) is used to model the self-heating (SH) in complex FinFET circuits. The NN training/testing datasets from 3-stage to 37-stage chain circuits in folded layout composed of inverter (INV)/NAND/NOR are simulated by our distributed Rth-Cth SPICE model [1, 2]. The interfacial thermal resistance [3], boundary scattering [4], alloy scattering [5], and layout dependence are considered. The NN interpretation by feature importance analysis is consistent with the thermal physics. Stage# is the most important feature of the NN prediction. Both via2 bundle positions and via2 numbers (via2#) are effective to reduce SH. As compared to SPICE, NN prediction in 37-stage INV chain computes 3×106 × faster with accuracy loss < 1°C. The high computation efficiency and high precision make NN feasible to predict chain circuits up to 40 stages, which cannot be simulated by SPICE due to long computation time.