학술논문

CFET Design Options, Challenges, and Opportunities for 3D Integration
Document Type
Conference
Source
2021 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2021 IEEE International. :3.1.1-3.1.4 Dec, 2021
Subject
Components, Circuits, Devices and Systems
Microprocessors
Layout
Field effect transistors
Computer architecture
Cost benefit analysis
Electron devices
Three-dimensional integrated circuits
Language
ISSN
2156-017X
Abstract
Design details of standard cell architectures using complementary field effect transistors (CFET) are explored. The primary structural elements of CFET are reviewed and the layout impact of several 2 nd -order technology constructs is analyzed. A manufacturability assessment and cost analysis of the resulting CFET technology-architecture definition is presented. Finally, the extendibility of CFET to 3.5-track cell height as well as higher-order 3D integration is explored.