학술논문
Fine-Pitch RDL Integration for Fan-Out Wafer-Level Packaging
Document Type
Conference
Author
Source
2020 IEEE 70th Electronic Components and Technology Conference (ECTC) Electronic Components and Technology Conference (ECTC), 2020 IEEE 70th. :1126-1131 Jun, 2020
Subject
Language
ISSN
2377-5726
Abstract
Fan-Out wafer-level packaging (FOWLP) semi-additive process (SAP) flow for three layers of redistribution layer (RDL) has been developed. Patched dicing lane design is adopted to improve RDL plating uniformity by ~40x, as measured by sheet resistance (Rs). We demonstrate warpage correction solution to improve pattern integrity despite tool handling limitations. We also demonstrate a CMP solution to improve 2/2um L/S RDL pattern integrity by >10x. We achieve RDL mechanical integrity through an integrated endpoint-detection-controlled wet etch solution to achieve