부산대학교 도서관

This paper describes the design and implementation of an X-band scalable $4\times 4$ element-level digital phased array module. The module consists of sixteen active antenna elements. Each of these elements includes one custom CMOS RF SoC and one custom GaAs switch frontend IC. The RF SoC is implemented using a 65-nm CMOS process. The T/R Switch frontend IC is implemented in a $0.15-\mu \mathrm{m}$ GaAs pHEMT process. The module also includes a digital signal processor implemented in an FPGA SoC device, and the required power supply subsystems. This module can be used to build a large hierarchical digital phased array through synchronizing four LO signals at system level. The built array serves as a tool for researching software-defined phased array radar and communication systems. This paper reports initial test results of this module. This module achieves a state-of-the-art 42-mm scalable tile thickness.