학술논문

Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility
Document Type
Periodical
Source
IEEE Transactions on Computers IEEE Trans. Comput. Computers, IEEE Transactions on. C-30(7):513-519 Jul, 1981
Subject
Computing and Processing
Bit slices
hardware description languages
microprogramming
simulation and modeling
Language
ISSN
0018-9340
1557-9956
2326-3814
Abstract
The microprogrammed filter engine (MICE) is a fast, microprogrammable processor built with ECL bit slices (Motorola ECL 10800 series) intended primarily to be used as an on-line data filtering engine for high energy physics experiments. In this note we describe the use of a hardware description language used to model and simulate the hardware during its development. We treat the problem of describing a pipelined, horizontal (112 bits wide) host machine, implemented using bit slices with considerable potential for parallelism. Several levels of modeling are conceptually applicable to a problem of this nature and the note describes the thorough process followed before we decided on a particular style of description and simulation.