부산대학교 도서관

Building clock trees for tight skew constraints of clock delivery networks is standard in the industry. Tight slew constraints of high-performance designs require post-processing techniques to satisfy slew constraints after clock tree synthesis (CTS). Post-processing adversely impacts the power dissipation. This paper proposes slew merging region CTS (SMRcts); a novel algorithm to satisfy bounded slew and skew constraints simultaneously during synthesis. Experimental results performed on International Symposium on Physical Design (ISPD) 2010 benchmarks using a 20-nm FinFET technology show an average reduction of 15% power over a bounded skew approach. Comparison to the ISPD 2010 CTS contest solutions in the literature shows SMRcts producing a 51% improvement in a utility metric. Scalability of SMRcts is demonstrated on ISPD 2013 benchmarks with up to 100k sinks.