학술논문
High performance and low leakage current InGaAs-on-silicon FinFETs with 20 nm gate length
Document Type
Conference
Author
Sun, X.; D'Emic, C.; Cheng, C.-W.; Majumdar, A.; Sun, Y.; Cartier, E.; Bruce, R. L.; Frank, M.; Miyazoe, H.; Shiu, K.-T.; Lee, S.; Rozen, J.; Patel, J.; Ando, T.; Song, W.-B.; Lofaro, M.; Krishnan, M.; Obrodovic, B.; Lee, K.-T.; Tsai, H.; Wang, W.-E.; Spratt, W.; Chan, K.; Yau, J.-B.; Hashemi, P.; Khojasteh, M.; Cantoro, M.; Ott, J.; Rakshit, T.; Zhu, Y.; Sadana, D.; Yeh, C.-C.; Narayanan, V.; Mo, R. T.; Heo, Y.-C.; Kim, D.-W.; Rodder, M. S.; Leobandung, E.
Source
2017 Symposium on VLSI Technology VLSI Technology, 2017 Symposium on. :T40-T41 Jun, 2017
Subject
Language
ISSN
2158-9682
Abstract
We report the fabrication of short-channel FinFETs on InGaAs-on-silicon wafers using the aspect ratio trapping (ART) technique. We demonstrate excellent short-channel control down to 20 nm gate length due to scaled fin width down to 9 nm and reduction of parasitic bipolar effect (PBE). PBE that plagues III-V NFETs with gate-all-around (GAA) or III-V-on-insulator (III-V-OI) structures can be significantly suppressed by optimized ART FinFET technology. We demonstrate record high on-current ION and low drain leakage current for short gate lengths in the 20–32 nm range for InGaAs-on-silicon NFETs.