학술논문
A Discrete-Time FFT Processor for Ultrawideband OFDM Wireless Transceivers: Architecture and Behavioral Modeling
Document Type
Periodical
Source
IEEE Transactions on Circuits and Systems I: Regular Papers IEEE Trans. Circuits Syst. I Circuits and Systems I: Regular Papers, IEEE Transactions on. 57(11):3011-3022 Nov, 2010
Subject
Language
ISSN
1549-8328
1558-0806
1558-0806
Abstract
A discrete-time (DT) fast Fourier transform (FFT) processor which enables an architectural improvement to ultrawide-bandwidth orthogonal frequency-division multiplexing (OFDM) receivers for use in low-power handheld applications is presented. The new architecture performs FFT demodulation of the OFDM signal in the DT signaling domain before analog-to-digital conversion. The approach significantly reduces the required number of bits in the analog-to-digital converter (ADC) while increasing receiver linearity and providing improved handling of narrow-band blockers. The processor is first implemented in simulation using a top-down methodology based on behavioral models which are developed to describe the circuit functions of the DT FFT processor. System simulation results show that the processor can be implemented with DT CMOS circuits having typical nonidealities while outperforming equivalent all-digital FFT processors. An improvement in dynamic range in the FFT processor and ADC from 35 to 54 dB is demonstrated through simulation.