학술논문

Hardware-level thread migration in a 110-core shared-memory multiprocessor
Document Type
Conference
Source
2013 IEEE Hot Chips 25 Symposium (HCS) Hot Chips 25 Symposium (HCS), 2013 IEEE. :1-27 Aug, 2013
Subject
Computing and Processing
System-on-chip
Multicore processing
Instruction sets
Hardware
Transistors
Crosstalk
Language
Abstract
Presents a collection of slides covering the following topics: hardware level thread migration via 110-core shared memory multiprocessing; system design of 110-core chip multiprocessors; execution migration strategies; costs and performance issues; on-chip traffic and communications; traffic pattern analysis; tread migration strategies; system architectures that support 110-core multiprocessing; memory management; and supported modes of migration.