학술논문
Optimal PD-SOI Technology for High Performance Applications
Document Type
Conference
Author
Source
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) VLSI Technology, Systems and Applications, 2008. VLSI-TSA 2008. International Symposium on. :93-94 Apr, 2008
Subject
Language
ISSN
1524-766X
Abstract
We present an optimal partially-depleted silicon-on-insulator (PD-SOI) platform, which demonstrates superior performance of SOI over Bulk technology. Device optimization is performed in terms of circuit switch speed and power consumption through channel and S/D engineering. Fundamental device characteristics, SRAM yields, reliability assessment, and physical IP qualification for our PD-SOI platform are all validated to demonstrate the feasibility for high performance applications. Performance comparison based on circuit simulation clearly shows the SOI advantage on area and power consumption. In addition, the strained-SOI (sSOI) technology is developed for further SOI performance enhancement.