학술논문
Circuit Performance Optimization in Advanced PD-SOI CMOS Development
Document Type
Conference
Author
Source
2007 IEEE International SOI Conference SOI Conference, 2007 IEEE International. :73-74 Oct, 2007
Subject
Language
ISSN
1078-621X
Abstract
Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that well-designed PAI improves circuit delay vs. leakage characteristics, while decreasing Tsi also reduces the propagation delay. We then present the optimized AC performance for a variety of circuits, as well as the DC performance, the SRAM characteristics, and the reliability assessment.