학술논문
Charge integrating ASIC with pixel level A/D conversion
Document Type
Conference
Author
Source
2007 IEEE Nuclear Science Symposium Conference Record Nuclear Science Symposium Conference Record, 2007. NSS '07. IEEE. 1:357-359 Oct, 2007
Subject
Language
ISSN
1082-3654
Abstract
A readout architecture appropriate for X-ray Imaging using charge integration has been designed. Each pixel consists of a capacitive transimpedance amplifier, a sample and hold circuit a comparator and an 8 bit DRAM. Pixel level A/D conversion and local storage of the digitized signal is performed. The target sensors are 100um x 100um CdTe pixel detectors and integration time of 1ms or less can be achieved. Special measures have been taken to minimize the gain fixed pattern noise and the reset noise, while purely digital correlation double sampling can be performed.