부산대학교 도서관

We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage (VTH) and supply voltage (VDD) scaling for ∼0.27× power reduction without sacrificing logic switching speed. With simultaneous VTH scaling, SRAM can operate at the same low VDD of 0.4V. Improved gate dielectric reliability raises maximum VDD for >70% speed boost when single thread performance is needed. Taking advantage of lower Cu wire resistance at 77 K, the repeaters for global signal propagation can be redesigned for 80% energy reduction. Increased thermal conductivity of silicon at low temperature reduces self-heating and further improves power efficiency. When refrigeration power is included, net power reduction can be achieved when cooling efficiency exceeds ∼ 50% of Carnot limit. We present effective VTH reduction methods for both nFET and pFET, critical for attaining high performance for cold CMOS.