부산대학교 도서관

The first level hardware muon trigger system in the barrel region of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN selects muon candidates with predefined transverse momentum and tags them with their Bunch Crossing number and geometrical coordinates. Four concentric layers of Resistive Plate Chambers (RPC) will be used as muon trigger detectors in the barrel region of the experiment for the Run4 of the High Luminosity LHC (HL-LHC), starting in 2029. The first level hardware muon trigger system for Run4 selects muon candidates using a coincidence-based algorithm on the four RPC layers. The usage of FPGA devices for both on-detector and off-detector trigger electronics is an ideal choice since it allows to take advantage of the FPGA increasing resources, performances, flexibility and radiation tolerance. The Data Collector and Transmitter (DCT) board will be used to readout the RPC detector. This board digitises up to 288 RPC front-end hit signals and measures the hit time of arrival with respect to the LHC 40 MHz bunch crossing clock. The DCT FPGA firmware implements a sub-nanosecond Time-to-Digital-Converter (TDC) used to time tag the incoming hit data. The TDC data are zero-suppressed to minimise the output bandwidth and then serially sent out to the barrel muon trigger off-detector electronics through optical fibres. The off-detector electronics execute the first level muon trigger algorithm and the RPC detector readout logic.