학술논문
A low power 40nm CMOS technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system
Document Type
Conference
Author
Watanabe, R.; Oishi, A.; Sanuki, T.; Kimijima, H.; Okamoto, K.; Fujita, S.; Fukui, H.; Yoshida, K.; Otani, H.; Morifuji, E.; Kojima, K.; Inohara, M.; Igrashi, H.; Honda, K.; Yoshimura, H.; Nakayama, T.; Miyake, S.; Hirai, T.; Iwamoto, T.; Nakahara, Y.; Kinoshita, K.; Morimoto, T.; Kobayashi, S.; Kyoh, S.; Ikeda, M.; Imai, K.; Iwai, M.; Nakamura, N.; Matsuoka, F.
Source
2008 IEEE International Electron Devices Meeting Electron Devices Meeting, 2008. IEDM 2008. IEEE International. :1-4 Dec, 2008
Subject
Language
ISSN
0163-1918
2156-017X
2156-017X
Abstract
Extremely high density CMOS technology for 40nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100kGate/mm 2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195μm 2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.