부산대학교 도서관

A comprehensive study was done regarding stabilities under simultaneous stress of light and negative gate bias ( $V_{\mathrm{ G}}$ )/positive drain bias ( $V_{\mathrm{ D}}$ ) in amorphous hafnium-indium–zinc-oxide thin-film transistors. Negative threshold voltage ( $V_{\mathrm {\mathbf {th}}}$ ) shift was observed in transfer characteristics after the stress. Through the consecutive stresses of ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{ S}}= 0$ V) and ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 0$ V, and $V_{\mathrm{S}}= 15$ V) under light illumination, it is found that the negative $V_{\mathrm {\mathbf {th}}}$ shift is affected only by $V_{\mathbf {G}}$ , because the drain current is determined by source-side energy barrier though drain-side energy band is locally lowered by $V_{\mathrm{D}}$ -induced drain-side trapped holes. Furthermore, the drain-side trapped holes increase ON-current by reducing channel resistance after channel accumulation. Gate-to-drain capacitance ( $C_{\mathrm {\mathbf {GD}}}$ ) was measured before/after the ( $V_{\mathrm{G}}= -5$ V, $V_{\mathrm{D}}= 15$ V, and $V_{\mathrm{S}}= 0$ V) stress to clarify the presence and distribution of the drain-side trapped holes. From $C_{\mathrm {\mathbf {GD}}}$ stretching out after the stress, it is revealed that the trapped holes introduce an additional capacitance by responding to the accumulated electrons and the capacitance is distributed according to the vertical electric field distribution of the stress.