학술논문

One-Transistor Poly-Si Memory Devices With Near-Zero Subthreshold Swing and Extended Retention Time
Document Type
Periodical
Author
Source
IEEE Electron Device Letters IEEE Electron Device Lett. Electron Device Letters, IEEE. 45(6):1008-1011 Jun, 2024
Subject
Engineered Materials, Dielectrics and Plasmas
Components, Circuits, Devices and Systems
Logic gates
Nonvolatile memory
Silicon
Hysteresis
Junctions
Transistors
Random access memory
Poly-Si
grain boundaries (GBs)
capacitorless 1T-DRAM
parasitic bipolar junction transistor (BJT)
near-zero subthreshold swing (NZESS)
memory window
retention
nonvolatile memory (NVM)
Language
ISSN
0741-3106
1558-0563
Abstract
The novel one-transistor (1T) poly-Si memory devices with a floating-body (FB) configuration have been fabricated and demonstrated with near-zero subthreshold swing (NZESS) characteristics and favorable retention time for the first time. The operational principle of the device involves positive feedback triggering the latch of the parasitic bipolar junction transistor (BJT) and the advantages of extended retention through the charge trap effect of grain boundaries (GBs) in poly-Si, resulting in a high State 1/State 0 sensing drain current ratio ( $\text{I}_{\text {S{1}}}/\text{I}_{\text {S{0}}}{)} > 10^{{4}}$ and a large memory window ~ 5V. The overlay of hysteresis transfer characteristics also validates repeatability. Remarkably, the proposed poly-Si NZESS memory devices exhibit a preliminary nonvolatile memory (NVM)-like retention time of 1000 seconds, surpassing conventional capacitorless 1T-DRAM. These findings suggest their potential as next-generation memory devices, suitable for DRAM and NVM applications.