학술논문
High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface
Document Type
Conference
Author
Shimojo, Yoshiro; Konno, Atsushi; Nishimura, Jun; Okada, Takayuki; Yamada, Yuki; Kitazaki, Soichiro; Furuhashi, Hironobu; Yamazaki, Soichi; Yahashi, Katsunori; Tomioka, Kazuhiro; Minami, Yoshihiro; Kanaya, Hiroyuki; Shuto, Susumu; Yamakawa, Koji; Ozaki, Tohru; Shiga, Hidehiro; Miyakawa, Tadashi; Shiratake, Shinichiro; Takashima, Daisaburo; Kunishima, Iwao; Hamamoto, Takeshi; Nitayama, Akihiro
Source
2009 Symposium on VLSI Technology VLSI Technology, 2009 Symposium on. :218-219 Jun, 2009
Subject
Language
ISSN
0743-1562
2158-9682
2158-9682
Abstract
Novel cell technologies are successfully developed for the world's highest-density and highest-speed 128Mb chain FeRAM™ with SDRAM-compatible 1.6GByte/s DDR2 interface. To overcome the signal window reduction due to the capacitor shrinkage, new cell technologies such as half-pitch layout with triangular capacitors, advanced nestled chain structure, high-density cover film and low-damage etching technique are established. New architecture with small bit line capacitance of 60fF is also installed [1]. With these new technologies, the cell signal window reaches 380 mV, which is sufficient for stable 128Mb 1T1C operation.