학술논문
A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes
Document Type
Conference
Author
Shiga, Hidehiro; Takashima, Daisaburo; Shiratake, Shinichiro; Hoya, Katsuhiko; Miyakawa, Tadashi; Ogiwara, Ryu; Fukuda, Ryo; Takizawa, Ryosuke; Hatsuda, Kosuke; Matsuoka, Fumiyoshi; Nagadomi, Yasushi; Hashimoto, Daisuke; Nishimura, Hisaaki; Hioka, Takeshi; Doumae, Sumiko; Shimizu, Shoichi; Kawano, Mitsumo; Taguchi, Toyoki; Watanabe, Yohji; Fujii, Shuso; Ozaki, Tohru; Kanaya, Hiroyuki; Kumura, Yoshinori; Shimojo, Yoshiro; Yamada, Yuki; Minami, Yoshihiro; Shuto, Susumu; Yamakawa, Koji; Yamazaki, Souichi; Kunishima, Iwao; Hamamoto, Takeshi; Nitayama, Akihiro; Furuyama, Tohru
Source
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers Solid-State Circuits Conference - Digest of Technical Papers, 2009. ISSCC 2009. IEEE International. :464-465,465a Feb, 2009
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
An application that takes advantage of FeRAM characteristics is replacing current DRAM, which then becomes high-performance nonvolatile RAM cache. This improves system performance for many kinds of computer systems, including mobile PCs, cellular phones, digital video products, and storage systems such as SSDs. However, the highest capacity in nonvolatile RAMs that allow frequent cache reads and writes is limited to 64Mb [1,2]. The maximum read bandwidth is limited to 400MB/s [3] and the write bandwidth is limited to 200MB/s [1] in nonvolatile memories reported to date.