학술논문
A 76 mm/sup 2/ 8 Mb chain ferroelectric memory
Document Type
Conference
Author
Source
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) Solid-state circuits conference Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International. :40-41 2001
Subject
Language
ISSN
0193-6530
Abstract
An 8 Mb chain FeRAM uses 0.25 /spl mu/m 2-metal CMOS technology. A one-pitch-shift cell realizes 5.2 /spl mu/m/sup 2/ cell area. A chain architecture with a hierarchical wordline scheme gives 76 mm/sup 2/ die. Random access time is 40 ns, and cycle time is 70 ns at 3.0 V.