학술논문
FPGA implementation of programmable pulse mode neural network with on chip learning
Document Type
Conference
Author
Source
International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on. :159-164 2006
Subject
Language
Abstract
This paper presents an implementation of a pulse mode multilayer neural network with on chip learning. Taking advantage of the compactness of the multiplierless solutions proposed in the literature, we apply a multiplierless architecture, in which the synapse is made up with a DDFS and the neuron uses a nonlinear adder. A programmable activation function is proposed by means of an adjustable pulse multiplier so that the activation function slope can be adjusted without any added hardware cost. The proposed architecture was tested in a signature recognition system. It shows good learning capability. The corresponding design was implemented into a Virtex II PRO XC2VP7 Xilinx FPGA