학술논문

An Ultra-low Specific On-resistance SiC LDMOS Using Double RESURF and Field Plate Techniques
Document Type
Conference
Source
2023 IEEE 15th International Conference on ASIC (ASICON) ASIC (ASICON), 2023 IEEE 15th International Conference on. :1-4 Oct, 2023
Subject
Components, Circuits, Devices and Systems
Performance evaluation
Silicon carbide
Surface resistance
Doping
Logic gates
Numerical simulation
Optimization
SiC
LDMOS
specific on-resistance
trench gate
RESURF
field plate
Language
ISSN
2162-755X
Abstract
In this article, a 1200V 4H-SiC power laterally diffused metal-oxide-semiconductor (LDMOS) device with ultra-low specific on-resistance is proposed. The proposed LDMOS combines field plate technology and reduced surface field (RESURF) technology to improve the surface electric field distribution of the drift region, significantly increase the doping concentration of the drift region, reduce the drift region resistance. The integration of trench gate and planar gate increases the current conduction path and optimizes the specific on-resistance (R on,sp ) of the device. The TCAD numerical simulation results show that the breakdown voltage (BV) of the proposed LDMOS and conventional LDMOS are 1225V and 1100V, respectively. The R on,sp of the proposed LDMOS is 2.78 mΩ•cm 2 , while the R on,sp of the conventional SiC LDMOS is 7.34 mΩ•cm 2 . Thus the R on,sp increased by more than 62.1%. In addition, the optimization of device parameters is also discussed. The proposed SiC LDMOS exhibits excellent static characteristics, which provides a new direction for the development of SiC LDMOS.