학술논문
An ultra dense trench-gated power MOSFET technology using a self-aligned process
Document Type
Conference
Author
Source
Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216) Power semiconductor devices and ICs Power Semiconductor Devices and ICs, 2001. ISPSD '01. Proceedings of the 13th International Symposium on. :147-150 2001
Subject
Language
ISSN
1063-6854
Abstract
An ultra dense trench technology is reported in this paper. This advanced technology employs a fully self-aligned contact process. As a result, the cell pitch of 30 V trench-gated power MOSFETs has been reduced to 1.1 um. The specific on-resistance (including the source metal spreading resistance) of the median die size device has been reduced to 0.18 mohm.cm/sup 2/ at a gate voltage of 10 V. The tradeoffs, which are given towards the optimization of ultra dense trench-gated device's on-resistance, "Miller" charge, and breakdown voltage, are presented.