학술논문

E-Test Validation of Space Error Budget and Metrology
Document Type
Periodical
Source
IEEE Transactions on Semiconductor Manufacturing IEEE Trans. Semicond. Manufact. Semiconductor Manufacturing, IEEE Transactions on. 35(3):478-484 Aug, 2022
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Lithography
Semiconductor materials
Metrology
Semiconductor device measurement
Resistance
Metals
Resists
Space error
edge placement error
electrical test device
voltage contrast
Language
ISSN
0894-6507
1558-2345
Abstract
The electrical validation of a generalized space error model is reported. This was achieved by comparing inline e-beam “direct” space metrology measurements with an end-of-line, yield-based, space error metric. This electrical test (e-test) of the space error is derived from the conductance of metallized test structures with programmed interlayer offsets between line and block layers used for patterning. Local space variation was extracted from voltage contrast arrays, and from inline metrology statistics. A good match was observed between the predicted space error from the weighted sum of the local and non-local terms, and the measured e-test space error. A model is proposed for the experimental validation of the local term (stochastic) of the space error model.