학술논문

The Generalization of Stage-Reduced STPS for Low-Loss Unequal 1 × 4 Phased Array Architecture for 5G IoT Applications
Document Type
Periodical
Source
IEEE Internet of Things Journal IEEE Internet Things J. Internet of Things Journal, IEEE. 11(11):19978-19987 Jun, 2024
Subject
Computing and Processing
Communication, Networking and Broadcast Technologies
Phased arrays
Phase shifters
Insertion loss
Internet of Things
5G mobile communication
Dipole antennas
Antenna radiation patterns
0.15-μm GaAs pHEMT
beamforming
ka-band
low loss
millimeter-wave (mm-Wave) circuits
phase shifter
phased-array
Language
ISSN
2327-4662
2372-2541
Abstract
In this work, the stage-reduced switched type phase shifter (STPS)-based low loss and unequal phased array architecture without any power consumption is presented for 5G Internet of Things application. Since phase difference between channels $(\beta )$ in $\beta \leq $ –90° and $\beta \geq 90^{\circ }$ range is rarely used in practice because the side-lobe of the antenna increases, phase shifter units are unequally designed for each channel so as to use only the – $90^{\circ }\leq \beta \leq 90^{\circ }$ region, which is a region with a small side-lobe. In practice, this stage-reduced STPS structure is generalized to be applied to $n$ -stage $1\times 4$ beamforming architecture. As an example, a 4-bits conventional phase shifter with 22.5° resolution is implemented using only 3-bits in 0.15- $\mu \text{m}$ GaAs pHEMT for 28-GHz 5G n257 band. Compared to the conventional structure, insertion loss is improved thanks to removing 0°/180° stage revealing the highest insertion loss among the conventional 4 stages. The measured average insertion loss of the stage-reduced STPS is –4.3 and –3.2 dB for channels 1 and 4 and channels 2 and 3, respectively. The side-lobe of the proposed phased array is also improved as much as 1.6 dB than that of conventional phased array architecture since the insertion loss of channels 1 and 4 located on the edge side is 1.1 dB higher than that of channels 2 and 3. The proposed stage-reduced STPS reveals figure of merit lower than -1 dB without using any power consumption. To the best of our knowledge, this STPS achieves the lowest insertion loss among the published GaAs/CMOS STPS over a similar frequency.