학술논문
A 3D Stackable 1T1C DRAM: Architecture, Process Integration and Circuit Simulation
Document Type
Conference
Author
Huang, Meng; Si, Shufang; He, Zheng; Zhou, Ying; Li, Sijia; Wang, Hong; Liu, Jinying; Xie, Dongsheng; Yang, Mengmeng; You, Kang; Choi, Chris; Tang, Yi; Li, Xiaojie; Qian, Shibing; Yang, Xiaodong; Hou, Long; Bai, Weiping; Liu, Zhongming; Tang, Yanzhe; Wu, Qiong; Wang, Yanqin; Dou, Tao; Kim, Jake; Wang, Gui-Lei; Baisp, Jie; Takao, Adachi; Zhao, Chao; Yoo, Abraham
Source
2023 IEEE International Memory Workshop (IMW) Memory Workshop (IMW), 2023 IEEE International. :1-4 May, 2023
Subject
Language
ISSN
2573-7503
Abstract
Continuous shrinking of dynamic random access memory $\langle$DRAM) feature size will inevitably hit unsurmountable barriers, such as sub-10 nm patterning issues, ultra-high aspect ratio (HAR) capacitor and narrow sensing margin, etc. One candidate of promising solutions is the innovation in architecture with three-dimensional (3D) horizontally stacked transistors with capacitors, similar with a 3D NAND-like architecture. However, the process integration scheme and circuit simulation on the 3D Stackable DRAM architecture have been barely reported. In this paper, we systematically introduced a 3D DRAM architecture, integration scheme for the first time. Then we further performed circuit simulation studies on the 3D DRAM, which in return confirm the feasibility of our proposed architecture and show great prospect in DRAM core timing optimization.