학술논문
Defect-Free Electroplating of High Aspect Ratio Through Silicon Vias: Role of Size and Aspect Ratio
Document Type
Conference
Author
Source
2019 International Wafer Level Packaging Conference (IWLPC) Wafer Level Packaging Conference (IWLPC), 2019 International. :1-6 Oct, 2019
Subject
Language
Abstract
We study the role of via size and aspect ratio in defect-free electroplating of through silicon vias in 3DICs. Using a level-set curvature enhanced adsorbate coverage model, we simulate the electroplating of vias of various sizes and aspect ratio by varying the overpotential and the initial copper concentration. We find that as the via size and aspect ratio increases, the filling fraction reduces and voids are formed in the vias. Increasing overpotential also reduces the filling fraction. We show that in all these cases, increasing the initial copper concentration can result in increased filling of the vias of higher aspect ratios.