학술논문

Multiscale Models for Electroplating of Through Silicon Vias
Document Type
Conference
Source
2018 International Wafer Level Packaging Conference (IWLPC) Wafer Level Packaging Conference (IWLPC), 2018 International. :1-9 Oct, 2018
Subject
Components, Circuits, Devices and Systems
Engineered Materials, Dielectrics and Plasmas
Engineering Profession
Additives
Ions
Adsorption
Through-silicon vias
Plating
Computational modeling
Kinetic theory
Through silicon via
multiscale modelling
DFT calculations
kinetic Monte Carlo.
Language
Abstract
We present multi-scale models providing guidelines for defect free growth of filling of through silicon vias (TSV) by electroplating. Using first-principles calculations, we understand the chemistry of the electroplating process. We use density functional theory calculations to identify the reaction mechanisms and calculate the reaction energies of the different additives i.e., chloride ion, suppressor, and accelerator in the plating solution. We also present a kinetic Monte Carlo model that can incorporate the chemical and transport properties of the ions and additives during the electroplating. We demonstrate the role of aspect ratio and attachment rates on defect-free bottom-up filling. These multiscale tools can provide the inputs for a continuum phase field model to predict the microstructure during TSV filling (not reported here).