부산대학교 도서관

This article describes a frequency-interleaved digital-to-analog conversion technique named bandwidth tripler with an image-rejection analog multiplexer (AMUX). The tripler extends the bandwidth of the parallelized sub-digital-to-analog converters (DACs) by three times in the frequency domain. Image rejection using the phase-shifted method reduces analog filters for combining divided sub-bands, which improves the signal quality and size of the analog circuits. Besides, the tripler outputs no spurious signals out of the target bandwidth. The AMUX for the tripler was fabricated in 180-nm CMOS technology. Pseudo-differential switches were used to reduce distortion, and a broadband termination circuit was inserted at the output of the AMUX to compensate for the limited performance of the CMOS devices. The fabricated AMUX was evaluated by S-parameter and time-domain measurements. The S-parameter measurement results demonstrated a bandwidth of 23.4 GHz. In addition, broadband signal generation for 30 Gbps PAM4 was demonstrated without using any equalization. The power consumption of the AMUX was only 49 mW. This high-speed performance is comparable to the conventional DACs fabricated using advanced CMOS processes.