학술논문

Cut and Forward: Safe and Secure Communication for FPGA System on Chips
Document Type
Periodical
Source
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 41(11):4052-4063 Nov, 2022
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Field programmable gate arrays
System-on-chip
Hardware acceleration
Switches
Security
Behavioral sciences
Safety
FPGA system-on-chip (SoC)
hardware security
mission-critical systems
on-chip communication
Language
ISSN
0278-0070
1937-4151
Abstract
Modern FPGA system on chips uses complex multimanager, multisubordinate on-chip communication networks. Processor cores, hardware accelerators, DMA engines, and other manager components actively access subordinate components like off-chip DRAM, on-chip memories, caches, and I/Os. On-chip communication networks are designed for high bandwidth and low latency. They use simple, fast transactions that largely assumes the managers cooperate. For example, it does not describe default mechanisms to ensure the safe behaviors of the managers using the on-chip interconnect. This lack of specification can lead to unpredictable behaviors: a single misbehaving, misconfigured, or malicious component can cause denial of service of shared resources. Clearly, this issue is critical in systems with safety and security constraints. Cut and forward is a novel switching method for multicomponent communication architectures on FPGA systems on chips (SoCs). Cut and forward leverages the programmability of FPGA SoCs to enable safe and secure bus access and is carefully designed to minimize its impact on performance and resource usage. Experiments show that Cut and forward ensures safety and security in realistic applications deployed on a commercial FPGA SoC from Xilinx including a popular deep neural network accelerator.