학술논문
A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology
Document Type
Conference
Author
Ek, Staffan; Karlsson, Patrik; Kampe, Andreas; Strandberg, Roland; Narayanan, Aravind Tharayil; Anderson, Martin; Dafallah, Hind; Daghbashyan, Mesrop; Nejad, Tayebeh Ghanavati; Hagglund, Robert; Ivanisevic, Nikola; Nilsson, Robert; Nygren, Peter; Palm, Mattias; Sall, Erik; Tao, Sha; Yee, My-Chien; Sundstrom, Lars
Source
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Solid State Circuits Conference (ESSCIRC), ESSCIRC 2022- IEEE 48th European. :237-240 Sep, 2022
Subject
Language
Abstract
This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a self-resetting differential comparator-based BBPD with low hysteresis and a dual DCO architecture for lowest phase noise at respective output frequency. The PLL is implemented in a 7 nm FinFET process with an area of 0.18 mm 2 and achieves