부산대학교 도서관

In this paper, we propose a practical error detection method for combinatorial circuits using three-site implications which satisfies safety integrity level ASIL-B of ISO 26262 standard. The proposed method finds implications which are invariant relationships among internal signals in a logic circuit for any input pattern, and adds checkers to confirm that the implications are satisfied during functional operation. While the checkers playa role of CED (Concurrent Error Detection), higher error detection coverage can be achieved by using three-site implications than only with two-site implications as is the case in previous works. However, as circuit size grows it becomes difficult to find out effective three-site implications in reasonable processing time due to a large number of candidate implications. In the proposed method, along with various speed up techniques utilizing commercial EDA tools, newly developed indexes to narrow down the search space in three-site implication extraction with minimum loss of error detection coverage can achieve reasonable processing time, error detection coverage and area overhead. As preliminary experiments with resynthesized ISCAS85 benchmark circuits, we confirmed that the error detection coverage using all three-site implications under the limit of 50% area overhead is 19.5% higher than only with two-site implications, and the checkers using three-site implications extracted by the proposed indexes can achieve 96% of the error detection coverage derived using all three-site implications. We also applied the proposed method to an industrial CPU core, tinyMicon MatisseCORE™, as complementary error detection of software-based diagnosis. Through this experiment, we confirmed that 90% diagnostic coverage, which is equivalent to ASIL-B requirement in ISO 26262 standard, can be achieved by the checkers added by the proposed method with 15.41 % area overhead. This result implies the proposed method can be applied to actual commercial products.