학술논문

A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips
Document Type
Periodical
Source
IEEE Transactions on Emerging Topics in Computing IEEE Trans. Emerg. Topics Comput. Emerging Topics in Computing, IEEE Transactions on. 8(3):591-601 Sep, 2020
Subject
Computing and Processing
Logic gates
Circuit faults
Power control
Built-in self-test
Integrated circuit modeling
Degradation
Logic BIST
low power test
scan design
scan-in power control
pseudo-random pattern
Language
ISSN
2168-6750
2376-4562
Abstract
High power dissipation in scan-based logic built-in self-test (LBIST) is a crucial issue that can cause over-testing, reliability degradation, chip damage, and so on. While many sophisticated approaches to low-power testing have been proposed in the past, it remains a serious problem to control the test power of LBIST to a predetermined appropriate level that matches the power requirements of the circuit-under-test. This paper proposes a novel power-control method for LBIST that can control the scan-shift power to an arbitrary level. The proposed method modifies pseudo-random patterns generated by an embedded test pattern generator (TPG) so that the modified patterns have the specific toggle rate without sacrificing fault coverage and test time. In order to evaluate the effectiveness of the proposed method, this paper shows not only simulation-based experimental results but also measurement results on test element group (TEG) chips.