학술논문

Decap Insertion With Local Cell Relocation Minimizing IR-Drop Violations and Routing DRVs
Document Type
Periodical
Source
IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 32(5):823-834 May, 2024
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Routing
Layout
Integrated circuit modeling
Heuristic algorithms
Capacitance
Runtime
Optimization
Decoupling capacitor (decap)
design rule violation (DRV)
dynamic IR-drop
machine learning
Language
ISSN
1063-8210
1557-9999
Abstract
Decoupling capacitor (decap) cells are inserted near function cells of high switching activities so that their IR-drop can be suppressed. Decaps become more complex these days while a number of metal layers are used for internal connection, thereby starting to manifest themselves as routing blockage. Postplacement decap insertion with both IR-drop violations and routing design rule violations (DRVs) being taken into account is addressed for the first time. Local cell relocation is performed to reduce the number of decaps in the actual decap insertion step. U-Net integrated with a graph convolutional network (GCN) is introduced to predict the DRV probability, which drives decap insertion. The problem of decap insertion is then formulated as mixed integer quadratically constrained programming (MIQCP) and a heuristic algorithm is presented for practical application. Experiments with a few test circuits demonstrate that the increase in routing DRV is reduced by 26% on average with no IR-drop violations, compared to conventional methods that do not explicitly consider DRVs. This brings a 60% reduction in routing runtime and a 33% improvement in total negative slack (TNS).