학술논문
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing
Document Type
Conference
Author
Source
2022 IEEE International Symposium on Circuits and Systems (ISCAS) Circuits and Systems (ISCAS), 2022 IEEE International Symposium on. :1556-1560 May, 2022
Subject
Language
ISSN
2158-1525
Abstract
In this work, we propose an energy-efficient 64$\times $ 64 compute-in-memory (CIM) SRAM macro using a 7T bit-cell in 65nm CMOS UMC PDK. It supports 4-bit inputs, 4-bit weights & 4-bit outputs and performs 4-bit MAC operations. It also supports multiple row activations performing 1024 4b$\times $4b multiply and accumulate (MAC) operations in one clock cycle. Inputs are realized by the number of pulses on the read wordline (RWL), which discharges read bitline (RBL) according to bitwise multiplication of weights & inputs. Outputs of 4 columns storing 4-bit weights are then combined via charge sharing to perform a binary-weighted average representing MAC operation, further quantized by a flash analog to digital converter (ADC) giving 4-bit output. The proposed CIM macro achieves an energy efficiency of 28.9 TOPS/W and throughput of 212.9 GOPS operating at supply voltage 1 V with a 2 GHz clock frequency.