학술논문

Evaluation of Power-of-two Quantization for Multiplier-less Near-Memory and In-Memory Computing Schemes for Biomedical Applications
Document Type
Conference
Source
2023 IEEE Nordic Circuits and Systems Conference (NorCAS) Nordic Circuits and Systems Conference (NorCAS), 2023 IEEE. :1-5 Oct, 2023
Subject
Communication, Networking and Broadcast Technologies
Components, Circuits, Devices and Systems
Computing and Processing
Robotics and Control Systems
Signal Processing and Analysis
Quantization (signal)
Costs
Neurons
Silicon-on-insulator
Computer architecture
In-memory computing
Hardware
artificial neural networks
log quantization
in-memory computing
near-memory computing
multiplier-less
arrhythmia detection
sleep-apnea detection
Language
Abstract
Embedded Artificial Intelligence and Artificial Neural Networks and their implementation at the edge, as close as possible to the sensors, is an opportunity to develop biomedical applications such as long-term monitoring or point-of-care devices, but the implementation of such networks is constrained by hardware limitations: battery life and power consumption as well as silicon area. This paper focuses on the hardware implementation cost of a neuron/perceptron. Two different solutions that respond to the challenge of reducing the hardware cost of embedded artificial intelligence neural networks and neurons are studied. The first solution studied is the replacement of multipliers by shifters allowed by the use of non-uniform powers-of-two quantization of the network weights, which is validated on three different classification cases (arrhythmia, sleep-apnea and image recognition). The second solution studied is a comparative study of the advantages and limitations of conventional von-Neumann and in/near-memory implementation of a neuron in terms of hardware implementation cost. Performance metrics are estimated in 28nm FDSOI technology.