부산대학교 도서관

In-memory computing (IMC) based on static random access memory (SRAM) is a promising solution to enable highly energy-efficient multiply-accumulate (MAC) operations for machine learning accelerators. In this paper, an in-SRAM computing technique is proposed by using a dual-six-transistor (dual-6T) SRAM cell. The dual-6T SRAM cell is composed of two conventional-6T-SRAM-cell-like 6T cells with split wordlines, achieving a compact array layout. With specialized coding, the dual-6T SRAM circuit is one of the few in-memory accelerators which support parallel MAC operations with both ternary activation and ternary weight. A $128\times 64$ memory array is implemented in a 55-nm low-power CMOS technology. Due to the compact bitcell topology and smart coding, the proposed dual-6T memory array achieves up to 635 TOPS/W energy efficiency @ 100 MHz and 38.84 TOPS/mm 2 peak area efficiency @ 350 MHz, which is competitive among the state-of-the-art in-memory computing MAC accelerators.