학술논문
A Novel architecture of a Low Power Folded Cascode OTA in 180nm CMOS process
Document Type
Conference
Author
Source
2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS) Advanced Computing and Communication Systems (ICACCS), 2021 7th International Conference on. 1:95-99 Mar, 2021
Subject
Language
ISSN
2575-7288
Abstract
Based on the 0.18 $\mu$ m 1.8V CMOS process, a novel architecture of folded cascode operational transconductance amplifier (OTA) is designed for a 10-bit pipelined A/D converter. Folded cascode OTA is the basic block of pipelined ADCs. Folded cascode OTA has a stable transient output of 1.6V. Simulation results show that the open-loop gain of the folded cascode OTA is 42.78 dB, Common-mode Rejection Ratio(CMRR) is 43.11 dB, the phase margin is 133 0 , and slew rate of 105.657V / $\mu$ s respectively. The power consumption of this amplifier is 13.64 $\mu$ W in the 180nm CMOS process. The simulated output waveform and frequency response is shown for a supply voltage of 1.8V.