학술논문

Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide
Document Type
Conference
Source
2012 IEEE International SOI Conference (SOI) SOI Conference (SOI), 2012 IEEE International. :1-2 Oct, 2012
Subject
Components, Circuits, Devices and Systems
Computing and Processing
Communication, Networking and Broadcast Technologies
Fields, Waves and Electromagnetics
Photonics and Electrooptics
Signal Processing and Analysis
Substrates
Logic gates
Implants
Doping
Current measurement
Silicon
Boron
Language
ISSN
1078-621X
Abstract
Planar fully depleted (FD) devices with thin Buried Oxide (BOX) offer the unique ability to incorporate effective back biasing which is a key enabler to build a versatile multi-Vt technology. From a dynamic standpoint, forward back bias lowers Vt and thus boost device performance, whereas reverse back bias increases Vt and thus decreases leakage [1]. From a static point of view the back gate allows fine Vt tuning. Here we propose and evaluate a back gate implant scheme that enables a full use of the back bias.