학술논문
A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits
Document Type
Conference
Author
Source
2015 IEEE International Electron Devices Meeting (IEDM) Electron Devices Meeting (IEDM), 2015 IEEE International. :7.3.1-7.3.4 Dec, 2015
Subject
Language
ISSN
2156-017X
Abstract
A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.