학술논문
An 8GHz floating-point multiply
Document Type
Conference
Author
Source
ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. Solid-State Circuits Solid-State Circuits Conference, 2005. Digest of Technical Papers. ISSCC. 2005 IEEE International. :374-604 Vol. 1 2005
Subject
Language
ISSN
0193-6530
2376-8606
2376-8606
Abstract
The implementation of the mantissa portion of a floating-point multiply (54/spl times/54b) is described. The 0.124mm/sup 2/ multiplier is implemented using limited switch dynamic logic and operates at speeds up to 8GHz in a 90nm SOI technology. The multiplier dissipates between 150mW and 1.8W as it scales between 2GHz and 8GHz.