부산대학교 도서관

Advances in materials growth techniques are enabling new device concepts, circuit approaches, and syste marchitectures to enhance and extend CM OS technology such as tunneling-based static random access memory [1] and steep subthreshold slope III–V tunneling field effect transistors (TFETs) [2]. TFETs are essentially gated Esaki (or backward) dio des operating in t he re verse (Zener) direction. Recently, the authors reported on record III–V tunnel diodes fabricated on Si [3] via a technique known as aspect ratio trapping (ART) [4, 5]. To the knowledge of the authors, the high PVCR (56) was the fourth highest reported for any tunnel diode structure on any substrate. In this stud y, th e au thors rep ort o n (i) th e tem peratured ependence of these devices, (ii) th e in sensitivity o f tunnel current (forward and Zener) to temperature, and (iii) the absence of mid-gap states in the excess current.